Publications
A 12-bit 78.8-dB SFDR 625-MS/s Two-step Pipelined-SAR ADC With Self-Adaptive Common-Mode Capacitor Multiplier
Authors: Zilin Jiang, Xuan Guo, Hanbo Jia, Jiawei Ding, Yulin Zhang, Kai Sun, Li Wang, Zunsong Yang, Franco Maloberti, and Xinyu Liu
IEEE Transactions on Circuits and Systems II: Express Briefs • 2026
A 12-bit 625-MS/s two-step pipelined-SAR ADC with a self-adaptive common-mode capacitor multiplier, achieving 78.8-dB SFDR.
A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS
Authors: Jiawei Ding, Xuan Guo, Shan Lu, Qing Su, Tao Liu, Hanbo Jia, Yihan Li, and Xinyu Liu
Microelectronics Journal • 2025-09
A 14-GS/s 8-bit time-interleaved SAR ADC implemented in 28-nm CMOS.